1. Field of the Invention
The present invention relates to a drive signal generating circuit for a sense amplifier, and particularly to a drive signal generating circuit for a sense amplifier which is compatible with a semiconductor memory device by driving the sense amplifier using both voltage applied from the outside and voltage outputted from a voltage generator.
2. Description of the Conventional Art
Referring to FIG. 1, there is shown a construction of a conventional semiconductor memory device. The conventional semiconductor memory device includes pull-up transistors PUTo to PUTn each having a gate to which a control signal SPB outputted from a sense amplifier control circuit is applied, and each having a source to which a voltage VCC applied from the outside is applied, respectively; PMOS latches PLo to PLn of the sense amplifier each having one end to which each drain of the pull-up transistors PUTo to PUTn is connected via a pair of bit lines BL and BLB; a memory cell array 10 being connected to word lines WLo to WLm, and connected to the other end of the PMOS latches PLo to PLn of the sense amplifier via the bit lines BL and BLB; NMOS latches NLo to NLn of the sense amplifier each having one end to which the memory cell array 10 is connected via the bit lines BL and BLB; and pull-down transistors PDTo to PDTn each having a drain to which each the other end of the NMOS latches NLo to NLn of the sense amplifier is connected, each having a gate to which a control signal SN outputted from the sense amplifier control circuit is applied, and each having a source to which a ground voltage Vss is applied, respectively.
PMOS latch PLo out of the PMOS latches PLo to PLn of the sense amplifier includes an PMOS transistor 20 having a source to which a drain of the pull-up transistor PUTo is connected via the bit line BLB, and having a drain to which the memory cell array 10 is connected via the bit line BLB; and an PMOS transistor 21 having a gate to which the drain of the NMOS transistor 20 is connected, having a source to which the drain of the pull-up transistor PUTo is connected via the bit line BL, and having a drain to which a gate of the NMOS transistor 20 is connected and further, the memory cell array 10 is connected via the bit line BL. The remaining PMOS latches of the sense amplifier are constructurally the same as the PMOS latch PLo of the sense amplifier.
The memory cell array 10 has a plurality of memory cells which are constructurally the same as the memory cell 11. The memory cell 11 includes an NMOS transistor 12 having a gate to which a word line WLo is connected and having a drain to which the bit line BL is connected; and a capacitor 13 having one end to which a source of the NMOS transistor 12 is connected, and having the other end to which ground voltage is applied.
NMOS latch NLo out of the NMOS latches NLo to NLn of the sense amplifier includes an NMOS transistor 30 having a drain to which the memory cell array 10 is connected via the bit line BLB, and having a source to which the drain of the pull-down transistor PDTo is connected via the bit line BLB; and an NMOS transistor 31 having a drain to which a gate of the NMOS transistor 30 is connected and further the memory cell array 10 is connected via the bit line BL, having a gate to which the drain of the NMOS transistor 30 is connected, and having a source to which the drain of the pull-down transistor PDTo is connected via the bit line BL. The remaining NMOS latches of the sense amplifier are constructurally the same as the NMOS latch NLo of the sense amplifier.
Here, the bit lines BL and BLB are generally precharged with a predetermined voltage VCC/2.
The detailed operation of the conventional semiconductor memory device will be explained.
First, in case of standby state, a control signal SPb of high level is applied to each gate of the pull-up transistors PUTo to PUTn, and a control signal SN of low level is applied to each gate of the pull-down transistors PDTo to PDTn. Accordingly, the pull-up transistors PUTo to PUTn and the pull-down transistors PDTo to PDTn are turned off, and the sense amplifier does not operate.
Whereas, in case of active state, the control signal SPb of low level is applied to each gate of the pull-up transistors PUTo to PUTn, and the control signal SN of high level is applied to each gate of the pull-down transistors PDTo to PDTn. Accordingly, the pull-up transistors PUTo to PUTn and the pulldown transistors PDTo to PDTn are turned on.
When a high level signal is applied to the word line WLo, the cells connected to the word line WLo are selected, and data which are stored in the selected cells are loaded to the bit line BL, thereby the loaded data are latched after being sensed by the PMOS and NMOS latches of the sense amplifier.
That is, when data of high level is stored in the capacitor 13 of the memory cell 11, the stored data of high level is loaded to the bit line BL and the NMOS transistor 30 is turned on, thereby the precharged bit line BLB is charged to low level. As a result, the difference between voltages charged to the bit lines BL and BLB is amplified by NMOS latch NLo. Whereas, when data of low level are stored in the capacitor 13 of the memory cell 11, the difference between voltages charged to the bit lines BL and BLB is amplified by the PMOS latch PLo of the sense amplifier, as shown above.
To reduce electric power of the semiconductor memory device, sensing current having large weight should be lessened, and to lessen the sensing current, voltage level supplied to each source of the pull-up transistors should be lowered.
However, in the conventional semiconductor memory device, when operating voltage of the sense amplifier is lowered, the semiconductor memory device does not operate in high speed because the performance of the sense amplifier is lowered, thereby the sensing speed is decreased.
Further, when voltage outputted from the voltage generator having lower voltage level than voltage applied from the outside is only used, as load in the voltage generator becomes very large, so designing circuits of the voltage generator is not easy. Additionally, as voltage outputted from the voltage generator is unstable in initial sensing state when sensing current amount is great, refresh characteristic of the memory cell is lowered.